Gate to GDSII. Place And Route Methodology

The e-book illustrates the implementation of a physical layout from a gate-level netlist. It emphasizes on the place and route methodology. The concepts are applicable to the place and route tools that you might be working with.

The e-book is currently under development. Recognising the rapid advancement in the place and route technology, I will release the chapter as and when it is available, rather than releasing the completed e-book at a much later date.

If you wish to be notified when a new chapter or a revision of a chapter is made available, please send me a mail at pnr@eda-utilities.com. Your feedback and suggestion are most welcome.


ChapterPreviewOrderRevision
Table of contentsDownloadFree1.0
PrefaceNot availableFree-
1. A quick tour from Gate to GDSDownloadFree1.0
2. Library and Data PreparationNot availableNot available-
3. Static Timing Analysis RevisitNot availableNot available-
4. Floor PlanningNot availableNot available-
5. Power PlanningNot availableNot available-
6. Physical SynthesisNot availableNot available-
7. Clock Tree SynthesisNot availableNot available-
8. Detailed RoutingNot availableNot available-
9. Hierarchical Place and RouteNot availableNot available-
10. Signal IntegrityNot availableNot available-
11. Low Power methodologyNot availableNot available-
12. Yield EnhancementNot availableNot available-
13. Physical VerificationNot availableNot available-
14. Post Layout VerificatinNot availableNot available-
Appendix I: Design For TestNot availableFree-